Digital circuits operate on bit signals having high and low states, often represented by “1”s and “0”s. The bit rate is referred to as the bit frequency, or data frequency where the bits represent data. In integrated circuit chips, it is common that sequential circuits operate at different frequencies (different clock rates) such that inputs of a second circuit operating at one frequency receive outputs of a first circuit operating at a different frequency. Where the second circuit operates at a higher frequency than the first circuit, it is quite simple to convert low frequency data stream to a high frequency data stream by simply inserting additional 0's into the low frequency stream. However, a reversal of that conversion (i.e., to convert a high frequency data stream to a low frequency data stream) is not so easy.
Consider a circuit that operates at a given clock rate set by a clock signal, CLOCK, has data bus carrying data bits, DATA, and a port carrying valid bits, VALID, identifying whether a corresponding data bit on the data bus represents real data. The number of bits in VALID equals the number of clock cycles. The VALID bit is true, or “1”, when the associated DATA bit on the data bus represents real data, and false, or “0”, when the DATA bit is not real data. The density of a data stream containing DATA is the number of appearances of 1's in VALID during some time period, T, divided by the number of clock cycles for that period. Thus the density is a number having a maximum value of 1.0 representing a maximal density when VALID=1 on each clock cycle. Where the time period T is fixed, the density may be expressed simply as the number, DENS, of appearances of 1's in the VALID signal during period T. Dividing DENS by the number of clock cycles during period T results in the actual density. For example, if there are 256 clock cycles in time period T and 205 of the VALID bits are 1's, the density may be expressed as DENS=205, which is a density of 205/256=0.8008.
Considering the case of converting a high frequency data stream to a low frequency data stream, if the density of the high frequency data stream is low enough, the conversion might be accomplished by data compression, namely eliminating DATA bits from the high frequency data stream having associated VALID=0 bits. For example, if a high frequency data stream contains 10 DATA bits, 0110010011, over a given period T, and the associated VALID bit stream is 1110111011, DENS=8, and the density of the bit stream is 0.8. At high frequency fHIGH, T=10/fHIGH. This high frequency data stream might be converted to a low frequency data stream by compressing the data to remove invalid data bits, forming the low frequency data stream containing as few as 8 data bits, 01101011 having an associated VALID bit stream, 11111111. However, this type of conversion is possible only if the density of the resulting low frequency data stream does not exceed 1.0, i.e., DENS≦8, meaning that fLOW must be at least as great as 0.8fHIGH (fLOW≧0.8fHIGH). If fLOW<0.8fHIGH in the example, frequency conversion by data compression cannot be accomplished. Instead, it is common to employ a de-serialization technique to split the high frequency data stream into a plurality of low frequency data streams which are then applied to the output circuit.
Even if two signals have the same frequency, they may phase-shifted from each other, particularly if they employ different clock generators. In such a case, there is a need to synchronize data streams.
The present invention is directed to converter circuit that can convert a high frequency data stream to a low frequency data stream and can correct for phase shift between data streams.